Sr. Design for Test (DFT) Engineer

A Sr. Design for Test (DFT) Engineer at Lightmatter plays a crucial role in ensuring high-performance ASIC designs. Their responsibilities include inserting DFT into ASIC designs, generating test patterns, and collaborating with Physical Design and RTL teams for effective bring-up and debugging. This role is essential in pushing the boundaries of AI data center infrastructure.

To qualify for the Sr. Design for Test (DFT) Engineer position at Lightmatter, candidates should possess a BS or higher in Electrical Engineering and have a minimum of 15 years of relevant industry experience. Familiarity with standard DFT CAD tools, scripting knowledge in Python or TCL, and experience in both ASIC and semi-custom COT flows are essential. Additionally, understanding DFT impacts on timing and physical design structures is important.

As a Sr. Design for Test (DFT) Engineer at Lightmatter, you will engage in projects focused on developing high-performance ASICs for advanced AI and HPC workloads. This includes overseeing DFT insertion, automated test pattern generation, and interfacing with various teams to ensure the highest quality of designs, ultimately transforming the landscape of computing with light.

Essential skills for a Sr. Design for Test (DFT) Engineer at Lightmatter include a profound understanding of DFT practices, proficiency with DFT CAD tools, and experience with scripting languages like Python and TCL. Critical collaboration and communication skills are also key, as the role interfaces across various functional teams within the company.

The work environment at Lightmatter for a Sr. Design for Test (DFT) Engineer is dynamic and collaborative. Employees enjoy a flexible, hybrid workplace model which fosters innovation and teamwork. The atmosphere encourages tackling complex challenges while making significant contributions to cutting-edge technology in AI data centers.

Lightmatter offers competitive compensation and an attractive benefits package that includes comprehensive health care, retirement savings matching, generous paid time off, training and development opportunities, and a stock option plan. Our commitment to employee welfare ensures you thrive both personally and professionally.

To apply for the Sr. Design for Test (DFT) Engineer position at Lightmatter, interested candidates should visit our careers page to submit their applications along with an updated resume and cover letter detailing their relevant experience and strengths. We encourage all qualified applicants to apply and join us in our mission to revolutionize the future of computing.

When asked about DFT insertion in ASIC designs, it's important to outline that the process involves embedding mechanisms such as scan chains, boundary scans, and Built-In Self-Test (BIST) structures into the design to facilitate testing after fabrication. You should also discuss how this improves testability and reliability.

In dealing with timing closure challenges, you should express your methodical approach to analyzing timing reports, identifying critical paths, and applying optimizations. Mention your collaboration with the design team to iterate on solutions, which reflects teamwork as a key competency in this role.

When discussing your experience with scripting for DFT flows, highlight specific languages like Python or TCL that you have used. Be ready to provide examples of how you've automated processes or improved efficiency through your scripts, demonstrating your proactive approach to problem-solving.

Be prepared to talk about real challenges you've encountered during previous chip tapeouts, such as timing violations or design rule violations. Describe the steps taken to analyze and resolve these issues, showing that you possess both technical expertise and a calm demeanor under pressure.

Discuss your strategies for ensuring effective post-silicon DFT bring-up and debugging. Mention your methodology in analyzing results from automated tests, working closely with ATE engineers, and systematically troubleshooting potential issues, which conveys your detail-oriented nature and teamwork.

When discussing your experience with ATE test program development, be specific about the types of ATE systems you've worked with. Describe how you created and implemented test programs tailored for DFT structures and how you collaborated with engineering teams to achieve thorough coverage during testing.

A good answer would involve mentioning specific fault modeling techniques you have utilized, such as stuck-at faults or transition faults. Discuss how you integrate these models into DFT processes to enhance defect coverage rates, showing your knowledge and application of industry standards.

In answering this question, emphasize your understanding of how SoC architecture can influence the DFT strategy. Talk about the importance of integrating DFT considerations early in the design stage to streamline the overall testing process and minimize the impact on performance.

Your motivation to stay updated could be explained by discussing regular attendance at industry conferences, participating in online courses, or actively engaging with technical literature. Sharing your network connections with peers also highlights your commitment to continuous professional development.

When asked about the most critical aspect of DFT, consider discussing the balance between comprehensive testing and minimal design impact. Highlight that thorough test coverage is essential for reliability and yield without compromising design performance or feasibility.