SOC Verification Engineer

Job Summary

A company is looking for a SOC Verification Engineer to join its team in advancing technological innovation.

Key Responsibilities:

• Develop and execute test plans, test benches, and verification environments for SoC-level verification using SystemVerilog and UVM methodologies
• Collaborate with RTL designers to define verification scope and coverage goals based on microarchitecture specifications
• Perform functional verification, block-level and full-chip simulations, and debug functional issues

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in digital design verification, preferably at the SoC level
• Strong expertise in SystemVerilog, UVM, and scripting languages (Python, Perl, or Tcl)
• Hands-on experience in coverage-driven verification and assertion-based verification
• Familiarity with industry-standard EDA tools and bus protocols such as AMBA, PCIe, and USB