Implement DFT architecture for high-performance compute designs
Design, implement, and validate SCAN, MBIST, and JTAG DFT structures
Collaborate with the post-silicon team to bring up test patterns on silicon
Required Qualifications
Bachelor's or M.S. in Computer Engineering or Electrical Engineering
7+ years of industry experience with DFT for high-performance ASICs
Hands-on experience with DFT generation tools and flows for large SOC/ASIC
Expertise in DFT techniques such as ATPG and Scan compression
Experience in debugging DFT test patterns on ATE to resolve silicon issues
Average salary estimate
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