Principal Packaging Engineer - job 1 of 3

Job Summary

A company is looking for a Principal Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology.

Key Responsibilities

• Innovate and enhance CoWoS packaging processes to improve chip performance, power efficiency, and reliability
• Collaborate with design, test, and manufacturing teams for seamless chip-package integration
• Lead failure analysis and drive yield improvements across packaging processes

Required Qualifications

• 15 years of hands-on experience in advanced semiconductor packaging and interconnect processes
• Proven expertise in CoWoS / FOCoS, with familiarity in EMIB, InFO, and advanced 2.5D/3D integration technologies
• Strong knowledge of thermal management, reliability testing, and signal/power integrity challenges
• Experience working with TSMC and leading OSATs
• Bachelor's or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field