DFT Engineer Level 3

Job Summary

A company is looking for a DFT (Design for Test) Engineer Level 3.

Key Responsibilities:

• Manage DFT aspects of ASIC Design with a strong understanding of digital design concepts
• Adhere to the ASIC development process and collaborate with various teams to achieve project goals
• Utilize VHDL, Verilog, or System Verilog for RTL coding and apply DFT methodologies effectively

Required Qualifications:

• Bachelor's degree in Electrical or Computer Engineering with 8+ years of experience, or a Master's degree with 6 years of experience
• Experience in the full product life cycle of ASIC Design
• Proficient in using Cadence and/or Mentor test insertion and ATPG tools
• Knowledge of hierarchical scan testing, IEEE standards, and test compression techniques
• Experience with memory BIST, logic BIST, and generating test patterns